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Bookmark or Share- Hardware Manual — NVDLA DocumentationNVDLA v1¶. This is the non-configurable “full-precision” version of NVDLA. The design code is in nvdlav1 branch. In-memory data formats – description of the in-memory format for weight and activation data.. Integrator’s Manual – a guide for SoC integrators, including a walk-through of the NVDLA build infrastructure, NVDLA’s testbenches, and synthesis scripts.
- NVDLA Index of DocumentationNVDLA Primer – an introduction to the concepts behind NVDLA, the solution that NVDLA provides, the basics of NVDLA’s architecture, and what’s included in the NVDLA release. Intended for audiences of all levels. Open Source Roadmap – a look into what’s next in NVDLA releases.. Hardware Manual – hardware documents. Software Manual – an exploration of the software ecosystem that ...
- Integrator’s Manual — NVDLA DocumentationTable 61 Clock and Reset Signals ¶; Signal Name. Description. Recommended Connection. dla_core_clk. Functional clock for NVDLA. Always ticking clock. dla_csb_clk. CSB bus clock for NVDLA configuration, same clock domain as host
- NVDLA Primer — NVDLA DocumentationThe Small system model in Fig. 1, below, shows an example of a headless NVDLA implementation while the Large System model shows a headed implementation.The Small model represents an NVDLA implementation for a more cost-sensitive purpose built device. The Large System model is characterized by the addition of a dedicated control coprocessor and high-bandwidth SRAM to support the NVDLA sub-system.
- Open Source Roadmap — NVDLA DocumentationOpen Source Roadmap¶. The open sourcing of the NVDLA core will occur over the course of the next two calendar quarters. The intent is to deliver a useable core early, with additional configurations and features following.
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